1. Technical Field
This invention relates generally to memory devices, and more particularly, to the configuration of a flash memory array.
2. Background Art
FIG. 1 illustrates a typical NOR memory array structure 20 in layout form. The layout structure 20 includes elongated, substantially parallel source/drain regions 22, each made up of alternating sources S and drains D, a channel region CR connecting each adjacent source S and drain D as shown. Each bit line B0, B1, B2, B3 is associated with a respective source/drain region 22 running therealong and contacting individual drains D of its associated source/drain region 22 by means of contacts 30. The word lines of the structure are shown at W0, W1, W2, W3, and are orthogonal with a bit lines B0, B1, B2, B3. The sources S of the source/drain regions 22 are connected together in a direction parallel to the word lines W0, W1, W2, W3 as shown in FIG. 1, being formed by a self-aligned-source (SAS) process as for example disclosed in U.S. Pat. No. 5,656,513, Nonvolatile Memory Cell Formed Using Self Aligned Source Implant, issued to Wang et al. on Aug. 12, 1997, herein incorporated by reference. Cells C1, C2, C3 . . . are formed at the intersections of word lines W0, W1, W2, W3 and bit lines B0, B1, B2, B3.
FIG. 2 is a sectional view of FIG. 1. As shown therein, a substrate 32 has a plurality of elongated, parallel trenches 34 formed therein, each trench 34 being filled with oxide 36. A dielectric layer 38 is disposed thereover, and metal bit lines 40 are formed above the dielectric layer 38 and connected to respective drains D by vias 42. Provided over this structure is another dielectric layer 44, on which additional elements of the array are provided.
It will be noted that the fabrication of the bit lines of the array of FIGS. 1 and 2 requires formation of individual vias 42 in thee dielectric layer 38 to contact the drains D as described above, followed by formation of individual bit lines in trenches in the dielectric layer 38 to contact the vias 42 so that contact is made between the bit lines B0, B1, B2, B3 and drains D. While this is a well-known approach, it will be understood that increased efficiency and simplicity of design and fabrication are desirable.
Therefore, what is needed is a memory array wherein improved design and fabrication are achieved.
The present invention is a memory device having a substrate, and a plurality of source/drain regions in the substrate, each comprising a plurality of alternating sources and drains. The substrate defines a plurality of trenches filled with oxide, each positioned between an adjacent pair of source/drain regions, so that each oxide region has respective source/drain regions on one and the other sides thereof. Further included are a plurality of word lines and a plurality of bit lines, each bit line comprising a conductive region in the substrate, with oxide in a trench overlying each bit line. Further included are a plurality of connecting conductive regions in the substrate and associated with each bit line, each bit line being connected to (i) the sources of the source of the source/region on one side of the oxide overlying that bit line by some of the connecting conductive regions associated with that bit line, and (ii) the drains of a source/drain region on the other side of the oxide overlying that bit line by others of the connecting conductive regions associated with that bit line. The connecting conductive regions associated with each bit line extend therefrom to the source/drain regions on one and the other side of the oxide overlying that line in an alternating manner along the bit line length.